HD64F3048VTF8 Datasheet, PDF (619/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
register has been modified. Normal execution of an access immediately after register modification
is not guaranteed.
Bits 7 to 4—Reserved: These bits always read 1. Writing is disabled.
Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in
RAM. When RAMS = 1, all flash memory block are program/erase-protected.
Bit 3: RAMS
0
1
Description
Emulation not selected
(Initial value)
Program/erase-protection of all flash memory blocks is disabled
Emulation selected
Program/erase-protection of all flash memory blocks is enabled
Bits 2 and 1—RAM2 and RAM1: These bits are used with bit 3 to reassign an area to RAM (see
table 18.5).
Bit 0—Reserved: This bit is readable/writable.
Table 18.5 RAM Area Setting
RAM Area
H'FFF000–H'FFF3FF
H'000000–H'0003FF
H'000400–H'0007FF
H'000800–H'000BFF
H'000C00–H'000FFF
Bit 3
RAMS
0
1
1
1
1
Bit 2
RAM2
0/1
0
0
1
1
Bit 1
RAM1
0/1
0
1
0
1
RAM Emulation Status
No emulation
Mapping RAM
Rev. 3.00 Sep 27, 2006 page 591 of 872
REJ09B0325-0300