HD64F3048VTF8 Datasheet, PDF (436/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
Contention between Buffer Register Write and Input Capture
If a buffer register is used for input capture buffering and an input capture signal occurs in the T₃
state of a write cycle, input capture takes priority and the write to the buffer register is not
performed. See figure 10.69.
Buffer register write cycle
T₁
T₂
T₃
φ
Address bus
BR address
Internal write signal
Input capture signal
GR
N
X
TCNT value
BR
M
N
Figure 10.69 Contention between Buffer Register Write and Input Capture
Rev. 3.00 Sep 27, 2006 page 408 of 872
REJ09B0325-0300