HD64F3048VTF8 Datasheet, PDF (381/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
Bit 2—Overflow Interrupt Enable (OVIE): Enables or disables the interrupt requested by the
OVF flag in TSR when OVF is set to 1.
Bit 2: OVIE
0
1
Description
OVI interrupt requested by OVF is disabled
OVI interrupt requested by OVF is enabled
(Initial value)
Bit 1—Input Capture/Compare Match Interrupt Enable B (IMIEB): Enables or disables the
interrupt requested by the IMFB flag in TSR when IMFB is set to 1.
Bit 1: IMIEB
0
1
Description
IMIB interrupt requested by IMFB is disabled
IMIB interrupt requested by IMFB is enabled
(Initial value)
Bit 0—Input Capture/Compare Match Interrupt Enable A (IMIEA): Enables or disables the
interrupt requested by the IMFA flag in TSR when IMFA is set to 1.
Bit 0: IMIEA
0
1
Description
IMIA interrupt requested by IMFA is disabled
IMIA interrupt requested by IMFA is enabled
(Initial value)
10.3 CPU Interface
10.3.1 16-Bit Accessible Registers
The timer counters (TCNTs), general registers A and B (GRAs and GRBs), and buffer registers A
and B (BRAs and BRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data
bus. These registers can be written or read a word at a time, or a byte at a time.
Figures 10.6 and 10.7 show examples of word access to a timer counter (TCNT). Figures 10.8 to
10.11 show examples of byte access to TCNTH and TCNTL.
Rev. 3.00 Sep 27, 2006 page 353 of 872
REJ09B0325-0300