HD64F3048VTF8 Datasheet, PDF (78/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 2 CPU
Table 2.9 System Control Instructions
Instruction
Size^*
Function
TRAPA
—
Starts trap-instruction exception handling
RTE
—
Returns from an exception-handling routine
SLEEP
—
Causes a transition to the power-down state
LDC
B/W
(EAs) → CCR
Moves the source operand contents to the condition code register.
The condition code register size is one byte, but in transfer from
memory, data is read by word access.
STC
B/W
CCR → (EAd)
Transfers the CCR contents to a destination location. The condition
code register size is one byte, but in transfer to memory, data is
written by word access.
ANDC
B
CCR ∧ #IMM → CCR
Logically ANDs the condition code register with immediate data.
ORC
B
CCR ∨ #IMM → CCR
Logically ORs the condition code register with immediate data.
XORC
B
CCR ⊕ #IMM → CCR
Logically exclusive-ORs the condition code register with immediate
data.
NOP
—
PC + 2 → PC
Only increments the program counter.
Note: * Size refers to the operand size.
B: Byte
W: Word
Rev. 3.00 Sep 27, 2006 page 50 of 872
REJ09B0325-0300