HD64F3048VTF8 Datasheet, PDF (528/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 13 Serial Communication Interface
Clock
An internal clock generated by the on-chip baud rate generator or an external clock input from the
SCK pin can be selected by setting the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. See
table 13.9. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin.
Eight clock pulses are output per transmitted or received character.
When the SCI operates on an internal clock, the serial clock outputs the clock signal at the SCK
pin. Eight clock pulses are output per transmitted or received character. When the SCI is not
transmitting or receiving, the clock signal remains in the high state. However, when receiving
only, overrun error may occur or the serial clock continues output until the RE bit clears at 0.
When transmitting or receiving in single characters, select the external clock.
Transmitting and Receiving Data
SCI Initialization (Synchronous Mode): Before transmitting or receiving, clear the TE and
RE bits to 0 in SCR, then initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0 before
following the procedure given below. Clearing the TE bit to 0 sets the TDRE flag to 1 and
initializes TSR. Clearing the RE bit to 0, however, does not initialize the RDRF, PER, FER, and
ORE flags and RDR, which retain their previous contents.
Figure 13.15 is a sample flowchart for initializing the SCI.
Rev. 3.00 Sep 27, 2006 page 500 of 872
REJ09B0325-0300