HD64F3048VTF8 Datasheet, PDF (238/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 8 DMA Controller
Bits 2 to 0—Data Transfer Select (DTS2, DTS1, DTS0): These bits select the data transfer
activation source. Some of the selectable sources differ between channels A and B.*
Note: * Refer to section 8.3.4, Data Transfer Control Registers (DTCR).
Bit 2: DTS2
0
1
Bit 1: DTS1
0
1
0
1
Bit 0: DTS0
0
1
0
1
0
1
0
1
Description
Compare match/input capture A interrupt from ITU
channel 0
(Initial value)
Compare match/input capture A interrupt from ITU
channel 1
Compare match/input capture A interrupt from ITU
channel 2
Compare match/input capture A interrupt from ITU
channel 3
Transmit-data-empty interrupt from SCI channel 0
Receive-data-full interrupt from SCI channel 0
Falling edge of DREQ input (channel B)
Transfer in full address mode (channel A)
Low level of DREQ input (channel B)
Transfer in full address mode (channel A)
The same internal interrupt can be selected as an activation source for two or more channels at
once. In that case the channels are activated in a priority order, highest-priority channel first. For
the priority order, see section 8.4.9, DMAC Multiple-Channel Operation.
When a channel is enabled (DTE = 1), its selected DMAC activation source cannot generate a
CPU interrupt.
Rev. 3.00 Sep 27, 2006 page 210 of 872
REJ09B0325-0300