HD64F3048VTF8 Datasheet, PDF (752/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Appendix A Instruction Set
Table A.3 Number of States per Cycle
Access Conditions
On-Chip
Supporting
Module
External Device
8-Bit Bus
16-Bit Bus
Cycle
On-Chip 8-Bit 16-Bit
Memory Bus Bus
2-State 3-State
Access Access
2-State 3-State
Access Access
Instruction fetch
S_I
2
6
3
4
Branch address read S_J
Stack operation
S_K
Byte data access
S_L
3
2
Word data access
S_M
6
4
Internal operation
S_N 1
1
1
1
Legend:
m: Number of wait states inserted into external device access
6 + 2m 2
3+m
6 + 2m
1
1
3+m
1
Rev. 3.00 Sep 27, 2006 page 724 of 872
REJ09B0325-0300