HD64F3048VTF8 Datasheet, PDF (801/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

EBR2—Erase Block Register 2
Appendix B Internal I/O Register
H'43
Flash memory
Bit
Initial value^*
Read/Write
7
SB7
0
R/W^*
6
SB6
0
R/W^*
5
SB5
0
R/W^*
4
SB4
0
R/W^*
3
SB3
0
R/W^*
2
SB2
0
R/W^*
1
SB1
0
R/W^*
0
SB0
0
R/W^*
Small block 7 to 0
0 Block SB7 to SB0 is not selected (Initial value)
1 Block SB7 to SB0 is selected
Note: * The initial value is H'00 in modes 5, 6, and 7 (on-chip flash memory enabled). In modes
1, 2, 3, and 4 (on-chip flash memory disabled), this register cannot be modified and is
always read as H'FF.
H8/3048F
H8/3048B mask ROM version
H8/3048F-ONE
H8/3048ZTAT
H8/3048 mask ROM version
H8/3047 mask ROM version
H8/3045 mask ROM version
H8/3044 mask ROM version
Include this register
Not include this register
Rev. 3.00 Sep 27, 2006 page 773 of 872
REJ09B0325-0300