HD64F3048VTF8 Datasheet, PDF (418/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
of the buffer setting, when the TCNT value is captured into GRA at input capture A, the previous
GRA value is simultaneously transferred to BRA. Figure 10.52 shows the transfer timing.
TCNT value
H'0180
H'0160
Counter cleared by
input capture B
H'0005
H'0000
TIOCB
TIOCA
GRA
BRA
GRB
H'0005
Time
H'0160
H'0005
H'0160
H'0180
Input capture A
Figure 10.51 Register Buffering (Example 2: Buffering of Input Capture Register)
φ
TIOC pin
Input capture
signal
TCNT
n
n+1
N
N+1
GR
M
n
n
N
BR
m
M
M
n
Figure 10.52 Input Capture and Buffer Transfer Timing (Example)
Rev. 3.00 Sep 27, 2006 page 390 of 872
REJ09B0325-0300