HD64F3048VTF8 Datasheet, PDF (132/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 5 Interrupt Controller
5.2.5 IRQ Sense Control Register (ISCR)
ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the
inputs
at
pins
IRQ
5
to
IRQ₀.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0

 IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
0
0
0
0
0
0
0
0
R/W
R/W R/W
R/W
R/W
R/W R/W R/W
Reserved bits
IRQ ₅ to IRQ₀ sense control
These bits select level sensing or falling-edge
sensing for IRQ ₅ to IRQ₀ interrupts
ISCR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: These bits can be written and read, but they do not select level or
falling-edge sensing.
Bits 5 to 0—IRQ₅ to IRQ₀ Sense Control (IRQ5SC to IRQ0SC): These bits select whether
interrupts IRQ₅ to IRQ₀ are requested by level sensing of pins IRQ₅ to IRQ₀, or by falling-edge
sensing.
Bits 5 to 0:
IRQ5SC to IRQ0SC
0
1
Description
Interrupts are requested when IRQ₅ to IRQ₀ inputs are low (Initial value)
Interrupts are requested by falling-edge input at IRQ to IRQ
5
0
Rev. 3.00 Sep 27, 2006 page 104 of 872
REJ09B0325-0300