HD64F3048VTF8 Datasheet, PDF (220/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 7 Refresh Controller
Contention between RTCNT Write and Increment
If an increment pulse occurs in the T₃ state of an RTCNT write cycle, writing takes priority and
RTCNT is not incremented. See figure 7.21.
RTCNT write cycle by CPU
T₁
T₂
T₃
φ
Address bus
Internal
write signal
RTCNT
input clock
RTCNT
RTCNT address
N
M
Counter write data
Figure 7.21 Contention between RTCNT Write and Increment
Rev. 3.00 Sep 27, 2006 page 192 of 872
REJ09B0325-0300