HD64F3048VTF8 Datasheet, PDF (119/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.1 Overview
5.1.1 Features
The interrupt controller has the following features:
• Interrupt priority registers (IPRs) for setting interrupt priorities
Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis
in interrupt priority registers A and B (IPRA and IPRB).
• Three-level masking by the I and UI bits in the CPU condition code register (CCR)
• Independent vector addresses
All interrupts are independently vectored; the interrupt service routine does not have to
identify the interrupt source.
• Seven external interrupt pins
NMI has the highest priority and is always accepted*; either the rising or falling edge can be
selected. For each of IRQ₀ to IRQ₅, sensing of the falling edge or level sensing can be selected
independently.
Note: * For the H8/3048F-ONE (single power supply with flash memory), the NMI input may
be prohibited. For details, refer to section 18.8.4, NMI Input Disable Conditions.
Rev. 3.00 Sep 27, 2006 page 91 of 872
REJ09B0325-0300