HD64F3048VTF8 Datasheet, PDF (598/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 17 RAM
17.1.1 Block Diagram
Figure 17.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Bus interface
SYSCR
H'FEF10^*
H'FEF12^*
H'FEF11^*
H'FEF13^*
On-chip RAM
H'FFF0E^*
H'FFF0F^*
Even addresses
Legend:
SYSCR: System control register
Odd addresses
Note: * This example is of the operating in mode 7. The lower 20 bits of the address are shown.
Figure 17.1 RAM Block Diagram
17.1.2 Register Configuration
The on-chip RAM is controlled by SYSCR. Table 17.1 gives the address and initial value of
SYSCR.
Table 17.1 System Control Register
Address^*
Name
H'FFF2
System control register
Note: * Lower 16 bits of the address.
Abbreviation R/W
SYSCR
R/W
Initial Value
H'0B
Rev. 3.00 Sep 27, 2006 page 570 of 872
REJ09B0325-0300