HD64F3048VTF8 Datasheet, PDF (498/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 13 Serial Communication Interface
Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an
overrun error.
Bit 5: ORER
Description
0
Receiving is in progress or has ended normally
(Initial value)^*1
[Clearing conditions]
• The chip is reset or enters standby mode.
• Software reads ORER while it is set to 1, then writes 0.
1
A receive overrun error occurred^*2
[Setting condition]
Reception of the next serial data ends when RDRF = 1.
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the ORER flag, which retains its
previous value.
2. RDR continues to hold the receive data before the overrun error, so subsequent receive
data is lost. Serial receiving cannot continue while the ORER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
Bit 4—Framing Error (FER): Indicates that data reception ended abnormally due to a framing
error in asynchronous mode.
Bit 4: FER
Description
0
Receiving is in progress or has ended normally
(Initial value)^*1
[Clearing conditions]
• The chip is reset or enters standby mode.
• Software reads FER while it is set to 1, then writes 0.
1
A receive framing error occurred^*2
[Setting condition]
The stop bit at the end of receive data is checked and found to be 0.
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the FER flag, which retains its previous
value.
2. When the stop bit length is 2 bits, only the first bit is checked. The second stop bit is not
checked. When a framing error occurs the SCI transfers the receive data into RDR but
does not set the RDRF flag. Serial receiving cannot continue while the FER flag is set
to 1. In synchronous mode, serial transmitting is also disabled.
Rev. 3.00 Sep 27, 2006 page 470 of 872
REJ09B0325-0300