HD64F3048VTF8 Datasheet, PDF (888/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Appendix C I/O Port Block Diagrams
PB ₆
Reset
R
Q
D
PB ₆ DDR
C
WPBD
Reset
R
Q
D
PB₆ DR
C
TPC
TPC
output
enable
Next data
WPB
Output
trigger
Bus controller
CS₇
output
Chip select
enable
Legend:
WPBD: Write to PBDDR
WPB: Write to port B
RPB: Read port B
RPB
Figure C.11 (c) Port B Block Diagram (Pin PB₆)
DMAC
DREQ0
input
Rev. 3.00 Sep 27, 2006 page 860 of 872
REJ09B0325-0300