HD64F3048VTF8 Datasheet, PDF (125/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 5 Interrupt Controller
Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ₀ interrupt requests.
Bit 7: IPRA7
0
1
Description
IRQ interrupt requests have priority level 0 (low priority)
0
IRQ₀ interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ₁ interrupt requests.
Bit 6: IPRA6
0
1
Description
IRQ₁ interrupt requests have priority level 0 (low priority)
IRQ interrupt requests have priority level 1 (high priority)
1
(Initial value)
Bit 5—Priority Level A5 (IPRA5): Selects the priority level of IRQ₂ and IRQ₃ interrupt requests.
Bit 5: IPRA5
0
1
Description
IRQ₂ and IRQ₃ interrupt requests have priority level 0 (low priority)
(Initial value)
IRQ and IRQ interrupt requests have priority level 1 (high priority)
2
3
Bit 4—Priority Level A4 (IPRA4): Selects the priority level of IRQ₄ and IRQ₅ interrupt requests.
Bit 4: IPRA4
0
1
Description
IRQ₄ and IRQ₅ interrupt requests have priority level 0 (low priority)
(Initial value)
IRQ and IRQ interrupt requests have priority level 1 (high priority)
4
5
Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WDT and refresh controller
interrupt requests.
Bit 3: IPRA3
0
1
Description
WDT and refresh controller interrupt requests have priority level 0 (low priority)
(Initial value)
WDT and refresh controller interrupt requests have priority level 1 (high
priority)
Rev. 3.00 Sep 27, 2006 page 97 of 872
REJ09B0325-0300