HD64F3048VTF8 Datasheet, PDF (306/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 9 I/O Ports
Mode 7 (Single-Chip Mode): Port 5 functions as an input/output port. A pin in port 5 becomes an
output port if the corresponding P5DDR bit is set to 1, and an input port if this bit is cleared to 0.
In modes 1 to 4, P5DDR always returns 1 when read. No value can be written to.
In modes 5 to 7, P5DDR is a write-only register. Its value cannot be read. All bits return 1 when
read.
P5DDR is initialized to H'FF in modes 1 to 4 and H'F0 in modes 5 to 7 by a reset and in hardware
standby mode. In software standby mode it retains its previous setting, so if a P5DDR bit is set to
1 while port 5 acts as an I/O port, the corresponding pin maintains its output state in software
standby mode.
Port 5 Data Register (P5DR)
P5DR is an 8-bit readable/writable register that stores output data for pins P5₃ to P5₀. While port 5
acts as an output port, the value of this register is output. When a bit in P5DDR is set to 1, if port 5
is read the value of the corresponding P5DR bit is returned. When a bit in P5DDR is cleared to 0,
if port 5 is read the corresponding pin level is read.
Bits 7 to 4 are reserved. They cannot be modified and are always read as 1.
Bit
7
6
5
4
3
2
1
0




P5 ₃
P5 ₂
P5 ₁
P5 ₀
Initial value
1
1
1
1
0
0
0
0
Read/Write




R/W
R/W
R/W R/W
Reserved bits
Port 5 data 3 to 0
These bits store data
for port 5 pins
P5DR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Rev. 3.00 Sep 27, 2006 page 278 of 872
REJ09B0325-0300