HD64F3048VTF8 Datasheet, PDF (419/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
Figure 10.53 shows an example in which GRB3 is buffered by BRB3 in complementary PWM
mode. Buffering is used to set GRB3 to a higher value than GRA3, generating a PWM waveform
with 0% duty cycle. The BRB3 value is transferred to GRB3 when TCNT3 matches GRA3, and
when TCNT4 underflows.
TCNT3 and
TCNT4 values
H'1FFF
GRA3
TCNT3
TCNT4
GRB3
H'0999
H'0000
BRB3
H'0999
GRB3 H'0999
H'1FFF
H'0999
H'1FFF
Time
H'0999
H'1FFF
H'0999
TIOCA₃
TIOCB₃
Figure 10.53 Register Buffering (Example 3: Buffering in Complementary PWM Mode)
Rev. 3.00 Sep 27, 2006 page 391 of 872
REJ09B0325-0300