HD64F3048VTF8 Datasheet, PDF (253/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 8 DMA Controller
Table 8.7 Register Functions in Idle Mode
Register
23
0
MAR
23
All 1s
7
0
IOAR
15
0
ETCR
Function
Activated by
SCI0 Receive-
Data-Full
Interrupt
Other
Activation
Destination
address
register
Source
address
register
Source
address
register
Destination
address
register
Transfer
counter
Transfer
counter
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
Initial Setting Operation
Destination or Held fixed
source address
Source or
destination
address
Number of
transfers
Held fixed
Decremented
once per
transfer until
H'0000 is
reached and
transfer ends
MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or
destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all
1s. MAR and IOAR are not incremented or decremented.
Figure 8.4 illustrates how idle mode operates.
MAR
Transfer
1 byte or word is
transferred per request
Figure 8.4 Operation in Idle Mode
IOAR
Rev. 3.00 Sep 27, 2006 page 225 of 872
REJ09B0325-0300