HD64F3048VTF8 Datasheet, PDF (427/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
Table 10.10 ITU Interrupt Sources
Channel
Interrupt
Source
Description
DMAC
Activatable
Priority^*
0
IMIA0
Compare match/input capture A0
Yes
High
IMIB0
Compare match/input capture B0
No
OVI0
Overflow 0
No
1
IMIA1
Compare match/input capture A1
Yes
IMIB1
Compare match/input capture B1
No
OVI1
Overflow 1
No
2
IMIA2
Compare match/input capture A2
Yes
IMIB2
Compare match/input capture B2
No
OVI2
Overflow 2
No
3
IMIA3
Compare match/input capture A3
Yes
IMIB3
Compare match/input capture B3
No
OVI3
Overflow 3
No
4
IMIA4
Compare match/input capture A4
No
IMIB4
Compare match/input capture B4
No
OVI4
Overflow 4
No
Low
Note: * The priority immediately after a reset is indicated. Inter-channel priorities can be
changed by settings in IPRA and IPRB.
Rev. 3.00 Sep 27, 2006 page 399 of 872
REJ09B0325-0300