HD64F3048VTF8 Datasheet, PDF (16/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

2.7.2 Effective Address Calculation ............................................................................. 58
2.8 Processing States............................................................................................................... 62
2.8.1 Overview.............................................................................................................. 62
2.8.2 Program Execution State...................................................................................... 62
2.8.3 Exception-Handling State .................................................................................... 63
2.8.4 Exception-Handling Sequences ........................................................................... 64
2.8.5 Bus-Released State............................................................................................... 65
2.8.6 Reset State............................................................................................................ 66
2.8.7 Power-Down State ............................................................................................... 66
2.9 Basic Operational Timing ................................................................................................. 67
2.9.1 Overview.............................................................................................................. 67
2.9.2 On-Chip Memory Access Timing........................................................................ 67
2.9.3 On-Chip Supporting Module Access Timing ...................................................... 68
2.9.4 Access to External Address Space ....................................................................... 69
Section 3 MCU Operating Modes .................................................................................. 71
3.1 Overview........................................................................................................................... 71
3.1.1 Operating Mode Selection ................................................................................... 71
3.1.2 Register Configuration......................................................................................... 72
3.2 Mode Control Register (MDCR) ...................................................................................... 72
3.3 System Control Register (SYSCR) ................................................................................... 73
3.4 Operating Mode Descriptions ........................................................................................... 75
3.4.1 Mode 1 ................................................................................................................. 75
3.4.2 Mode 2 ................................................................................................................. 75
3.4.3 Mode 3 ................................................................................................................. 75
3.4.4 Mode 4 ................................................................................................................. 76
3.4.5 Mode 5 ................................................................................................................. 76
3.4.6 Mode 6 ................................................................................................................. 76
3.4.7 Mode 7 ................................................................................................................. 76
3.5 Pin Functions in Each Operating Mode ............................................................................ 77
3.6 Memory Map in Each Operating Mode ............................................................................ 77
Section 4 Exception Handling ......................................................................................... 81
4.1 Overview........................................................................................................................... 81
4.1.1 Exception Handling Types and Priority............................................................... 81
4.1.2 Exception Handling Operation............................................................................. 81
4.1.3 Exception Vector Table ....................................................................................... 82
4.2 Reset.................................................................................................................................. 84
4.2.1 Overview.............................................................................................................. 84
4.2.2 Reset Sequence .................................................................................................... 84
4.2.3 Interrupts after Reset............................................................................................ 87
Rev. 3.00 Sep 27, 2006 page xiv of xxvi