HD64F3048VTF8 Datasheet, PDF (746/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Appendix A Instruction Set
7. System control instructions
Mnemonic
Operation
Addressing Mode and
Instruction Length (bytes)
Condition Code
No. of
States^*1
TRAPA #x:2
 PC → @−SP,
CCR → @−SP,
<vector> → PC
RTE
 CCR ← @SP+,
PC ← @SP+
SLEEP
 Transition to power-
down state
LDC #xx:8, CCR
LDC Rs, CCR
LDC @ERs, CCR
LDC @(d:16, ERs), CCR
LDC @(d:24, ERs), CCR
LDC @ERs+, CCR
B #xx:8 → CCR
B Rs8 → CCR
W @ERs → CCR
W @(d:16, ERs) → CCR
W @(d:24, ERs) → CCR
W @ERs → CCR,
ERs32+2 → ERs32
LDC @aa:16, CCR
LDC @aa:24, CCR
STC CCR, Rd
STC CCR, @ERd
STC CCR, @(d:16, ERd)
STC CCR, @(d:24, ERd)
STC CCR, @–ERd
W @aa:16 → CCR
W @aa:24 → CCR
B CCR → Rd8
W CCR → @ERd
W CCR → @(d:16, ERd)
W CCR → @(d:24, ERd)
W ERd32−2 → ERd32,
CCR → @ERd
STC CCR, @aa:16
STC CCR, @aa:24
ANDC #xx:8, CCR
ORC #xx:8, CCR
XORC #xx:8, CCR
NOP
W CCR → @aa:16
W CCR → @aa:24
B CCR∧#xx:8 → CCR
B CCR∨#xx:8 → CCR
B CCR⊕#xx:8 → CCR
 PC ← PC+2
2
2
4
6
10
4
6
8
2
4
6
10
4
6
8
2
2
2
I HNZVC
2 1      14 16
10
 2
2
2
6
8
12
8
8
10
 2
 6
 8
      12
 8
 8
      10
2
2
2
2  2
Rev. 3.00 Sep 27, 2006 page 718 of 872
REJ09B0325-0300