HD64F3048VTF8 Datasheet, PDF (892/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Appendix D Pin States
Pin Name Mode
Reset
Hardware Software
Standby Standby
Mode
Mode
Bus-
Released
Mode
Program
Execution,
Sleep Mode
P9₅ to P9₀ 1 to 7
T
T
keep
keep^*1
I/O port
PA₃ to PA₀ 1 to 7
T
T
keep
keep^*1
I/O port
PA₆ to PA₄ 3, 4, 6
T^*4
T
H
H
CS₆ to CS₄
(CS output) (CS output) (CS output)
T (address
output)
keep
(otherwise)
T (address
output)
keep
(otherwise)
A₂₃ to A₂₁
(address
output)
I/O port
(otherwise)
1, 2, 5, 7
T^*4
T
keep
keep^*1
I/O port
PA
3, 4, 6
L^*4
T
T
T
A
7
20
1, 2, 5, 7
T^*4
T
keep
keep^*1
I/O port
PB₇,
1 to 7
T
PB to PB
5
0
PB
3, 4, 6
T
6
T
keep
keep^*1
I/O port
T
H
H
CS
7
(CS output) (CS output) (CS output)
keep
keep
I/O port
(otherwise) (otherwise) (otherwise)
1, 2, 5, 7
T
T
keep
keep^*1
I/O port
Legend:
H: High
L:
Low
T:
High-impedance state
keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register bit
Notes: 1. The bus cannot be released in mode 7.
2. Output is low only for reset by WDT overflow.
This RESO output function is only for the mask ROM, ZTAT, and flash memory (dual
power supply).
3. During direct power supply, oscillation damping time is “H” or “T”.
4. During direct power supply, oscillation damping time differs between “H”, “L” and “T”.
Rev. 3.00 Sep 27, 2006 page 864 of 872
REJ09B0325-0300