HD64F3048VTF8 Datasheet, PDF (474/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 12 Watchdog Timer
12.2.3 Reset Control/Status Register (RSTCSR)
RSTCSR is an 8-bit readable and writable register that indicates when a reset signal has been
generated by watchdog timer overflow, and controls external output of the reset signal.
Bit
7
6
5
4
3
2
1
0
WRST RSTOE 





Initial value
0
0
1
1
1
1
1
1
Read/Write R/(W)^* R/W






Reserved bits
Reset output enable
Enables or disables external output of the reset signal
Watchdog timer reset
Indicates that a reset signal has been generated
Notes: The method for writing to RSTCSR is different from that for general registers to prevent
inadvertent overwriting. For details see section 12.2.4, Notes on Register Rewriting.
* Only 0 can be written in bit 7, to clear the flag.
Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by
reset signals generated by watchdog timer overflow.
Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signal resets the entire chip
internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to
initialize external system devices. Note that there is no RESO pin in the versions with on-chip
flash memory.
Bit 7
WRST
0
1
Description
[Clearing conditions]
• Reset signal at RES pin.
• Read WRST when WRST = 1, then write 0 in WRST.
(Initial value)
[Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer operation
Rev. 3.00 Sep 27, 2006 page 446 of 872
REJ09B0325-0300