HD64F3048VTF8 Datasheet, PDF (414/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
Example of Phase Counting Mode
Figure 10.44 shows an example of operations in phase counting mode. Table 10.9 lists the up-
counting and down-counting conditions for TCNT2.
In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The
phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must
also be at least 1.5 states, and the pulse width must be at least 2.5 states. See figure 10.45.
TCNT2 value
Counting up
Counting down
TCLKB
Time
TCLKA
Figure 10.44 Operation in Phase Counting Mode (Example)
Table 10.9 Up/Down Counting Conditions
Counting Direction Up-Counting
TCLKB
TCLKA
↑
High _↓
Low
Low _↑
High _↓
Down-Counting
High _↓
Low
↓
Low _↑
↑
High
Phase
difference
Phase
difference
Pulse width
Pulse width
TCLKA
TCLKB
Overlap
Overlap
Phase difference and overlap: at least 1.5 states
Pulse width:
at least 2.5 states
Figure 10.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Rev. 3.00 Sep 27, 2006 page 386 of 872
REJ09B0325-0300