HD64F3048VTF8 Datasheet, PDF (841/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Appendix B Internal I/O Register
SSR—Serial Status Register
H'B4
Bit
Initial value
Read/Write
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
4
3
ORER FER/ERS PER
0
0
0
R/(W)* R/(W)* R/(W)*
2
TEND
1
R
1
MPB
0
R
SCI0
0
MPBT
0
R/W
Multiprocessor bit
0 Multiprocessor bit value in
receive data is 0
1 Multiprocessor bit value in
receive data is 1
Multiprocessor bit transfer
0 Multiprocessor bit value in
transmit data is 0
1 Multiprocessor bit value in
transmit data is 1
Parity error
0 [Clearing conditions]
Reset or transition to standby mode.
Read PER when PER = 1, then write 0
in PER.
1 [Setting condition]
Parity error: (parity of receive data does
not match parity setting O/E bit in SMR)
Transmit end
0 [Clearing conditions]
Read TDRE when TDRE = 1, then write 0 in TDRE.
The DMAC writes data in TDR.
1 [Setting conditions]
Reset or transition to standby mode.
TE is cleared to 0 in SCR and FER/ERS is
cleared to 0.
TDRE is 1 when last bit of 1-byte serial character
is transmitted.
Framing error (for SCI0)
0 [Clearing conditions]
Reset or transition to standby mode.
Read FER when FER = 1, then write 0 in FER.
1 [Setting condition]
Framing error (stop bit is 0)
Receive data register full
0 [Clearing conditions]
Reset or transition to standby mode.
Read RDRF when RDRF = 1, then write 0 in
RDRF.
The DMAC reads data from RDR.
1 [Setting condition]
Serial data is received normally and transferred
from RSR to RDR
Error signal status (for smart card interface)
0 [Clearing conditions]
Reset or transition to standby mode.
Read ERS when ERS = 1, then write 0 in ERS.
1 [Setting condition]
A low error signal is received.
Overrun error
0 [Clearing conditions]
Reset or transition to standby mode.
Read ORER when ORER = 1, then write 0 in
ORER.
1 [Setting condition]
Overrun error (reception of next serial data
ends when RDRF = 1)
Transmit data register empty
0 [Clearing conditions]
Read TDRE when TDRE = 1, then write 0 in TDRE.
The DMAC writes data in TDR.
1 [Setting conditions]
Reset or transition to standby mode.
TE is 0 in SCR
Data is transferred from TDR to TSR, enabling new
data to be written in TDR.
Note: * Only 0 can be written, to clear the flag.
Rev. 3.00 Sep 27, 2006 page 813 of 872
REJ09B0325-0300