HD64F3048VTF8 Datasheet, PDF (135/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 5 Interrupt Controller
5.3.2 Internal Interrupts
Thirty internal interrupts are requested from the on-chip supporting modules.
• Each on-chip supporting module has status flags for indicating interrupt status, and enable bits
for enabling or disabling interrupts.
• Interrupt priority levels can be assigned in IPRA and IPRB.
• ITU and SCI interrupt requests can activate the DMAC, in which case no interrupt request is
sent to the interrupt controller, and the I and UI bits are disregarded.
5.3.3 Interrupt Vector Table
Table 5.3 lists the interrupt sources, their vector addresses, and their default priority order. In the
default priority order, smaller vector numbers have higher priority. The priority of interrupts other
than NMI can be changed in IPRA and IPRB. The priority order after a reset is the default order
shown in table 5.3.
Rev. 3.00 Sep 27, 2006 page 107 of 872
REJ09B0325-0300