HD64F3048VTF8 Datasheet, PDF (549/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 14 Smart Card Interface
14.2.3 Serial Mode Register (SMR)
Bit 7 of SMR has a different function in smart card interface mode. The related serial control
register (SCR) changes from bit 1 to bit 0. However, this function does not exist in the flash
memory version.
Bit
Initial value
Read/Write
7
GM
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Bit 7—GSM Mode (GM): Set at 0 when using the regular smart card interface. In GSM mode,
set to 1. When transmission is complete, initially the TEND flag set timing appears followed by
clock output restriction mode. Clock output restriction mode comprises serial control register bit 1
and bit 0.
Bit 7: GM
0
1
Description
Using the regular smart card interface mode
• The TEND flag is set 12.5 etu after the beginning of the start bit
• Clock output on/off control only
Using the GSM mode smart card interface mode
• The TEND flag is set 11.0 etu after the beginning of the start bit
• Clock output on/off and fixed-high/fixed-low control
(set by SCR)
(Initial value)
Bits 6 to 0—Operate in the same way as for the normal SCI.
For details, see section 13.2.5, Serial Mode Register (SMR).
Rev. 3.00 Sep 27, 2006 page 521 of 872
REJ09B0325-0300