HD64F3048VTF8 Datasheet, PDF (420/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
10.4.9 ITU Output Timing
The ITU outputs from channels 3 and 4 can be disabled by bit settings in TOER or by an external
trigger, or inverted by bit settings in TOCR.
Timing of Enabling and Disabling of ITU Output by TOER
In this example an ITU output is disabled by clearing a master enable bit to 0 in TOER. An
arbitrary value can be output by appropriate settings of the data register (DR) and data direction
register (DDR) of the corresponding input/output port. Figure 10.54 illustrates the timing of the
enabling and disabling of ITU output by TOER.
T₁
T₂
T₃
φ
Address bus
TOER address
TOER
ITU output pin
Timer output
I/O port
ITU output
Generic input/output
Figure 10.54 Timing of Disabling of ITU Output by Writing to TOER (Example)
Rev. 3.00 Sep 27, 2006 page 392 of 872
REJ09B0325-0300