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HD64F3048VTF8 Datasheet, PDF (201/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip
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Section 7 Refresh Controller
Table 7.5 Address Multiplexing
Address Pins
A23 to
A10
AAAAAAAAAA
9
8
7
6
5
4
3
2
1
0
Address signals during row
address output
A23 to A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A
10
Address signals M9/M8 = 0 A23 to A9 A9 A16 A15 A14 A13 A12 A11 A10 A0
during column
A10
address output
M9/M8 = 1 A to A A A A A A A A A A
23
18
17
16
15
14
13
12
11
10
0
A10
φ
Address
bus
A23 to A 9 , A 0
A8 to A 1
T1
T2
T3
A 23 to A 9, A 0
A 8 to A1
Row address
a. M9/M8 = 0
A16 to A9
Column address
T1
T2
T3
φ
Address
bus
A 23 to A10, A 0
A9 to A 1
A 9 to A1
A 23 to A10, A 0
A18 to A10
Row address
Column address
b. M9/M8 = 1
Figure 7.4 Multiplexed Address Output (Example without Wait States)
Rev. 3.00 Sep 27, 2006 page 173 of 872
REJ09B0325-0300
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