HD64F3048VTF8 Datasheet, PDF (197/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

7.3 Operation
Section 7 Refresh Controller
7.3.1 Overview
One of three functions can be selected for the H8/3048B Group refresh controller: interfacing to
DRAM connected to area 3, interfacing to pseudo-static RAM connected to area 3, or interval
timing. Table 7.3 summarizes the register settings when these three functions are used.
Table 7.3 Refresh Controller Settings
Register Settings
RFSHCR SRFMD
PSRAME
DRAME
CAS/WE
M9/M8
RFSHE
RCYCE
RTCOR
RTMCSR
CKS2 to
CKS0
CMF
CMIE
P8DDR
P8₁DDR
DRAM Interface
Selects self-refresh
mode
Cleared to 0
Set to 1
Selects 2CAS or
2WE mode
Selects column
addressing mode
Selects RFSH signal
output
Selects insertion of
refresh cycles
Refresh interval
setting
Usage
PSRAM Interface
Selects self-refresh
mode
Set to 1
Cleared to 0
—
—
Selects RFSH signal
output
Selects insertion of
refresh cycles
Refresh interval
setting
Interval Timer
Cleared to 0
Cleared to 0
Cleared to 0
—
—
Cleared to 0
—
Interrupt interval
setting
Set to 1 when
RTCNT = RTCOR
Cleared to 0
Set to 1 (CS₃ output)
Set to 1 when
RTCNT = RTCOR
Cleared to 0
Set to 1 (CS₃ output)
Set to 1 when
RTCNT = RTCOR
Enables or disables
interrupt requests
Set to 0 or 1
ABWCR
ABW3
Cleared to 0
—
—
Rev. 3.00 Sep 27, 2006 page 169 of 872
REJ09B0325-0300