HD64F3048VTF8 Datasheet, PDF (842/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Appendix B Internal I/O Register
RDR—Receive Data Register
H'B5
SCI0
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Serial receive data
SCMR—Smart Card Mode Register
Bit
7
6
5



Initial value
1
1
1
Read/Write



H'B6
SCI0
4
3
2
1
0

SDIR SINV

SMIF
1
0
0
1
0

R/W R/W

R/W
Smart card interface mode select
0 Smart card interface function is disabled (Initial value)
1 Smart card interface function is enabled
Smart card data invert
0 Unmodified TDR contents are transmitted (Initial value)
Received data is stored unmodified in RDR
1 Inverted TDR contents are transmitted
Received data are inverted before storage in RDR
Smart card data transfer direction
0 TDR contents are transmitted LSB-first (Initial value)
Received data is stored LSB-first in RDR
1 TDR contents are transmitted MSB-first
Received data is stored MSB-first in RDR
Rev. 3.00 Sep 27, 2006 page 814 of 872
REJ09B0325-0300