HD64F3048VTF8 Datasheet, PDF (134/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 5 Interrupt Controller
IRQnSC
IRQnE
IRQn input
Edge/level
sense circuit
IRQnF
S
Q
R
IRQn interrupt
request
Clear signal
Note: n = 5 to 0
Figure 5.2 Block Diagram of Interrupts IRQ₀ to IRQ₅
Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF).
φ
IRQn
input pin
IRQnF
Note: n = 5 to 0
Figure 5.3 Timing of Setting of IRQnF
Interrupts IRQ₀ to IRQ₅ have vector numbers 12 to 17. These interrupts are detected regardless of
whether the corresponding pin is set for input or output. When using a pin for external interrupt
input, clear its DDR bit to 0 and do not use the pin for chip select output, refresh output, or SCI
input or output.
Rev. 3.00 Sep 27, 2006 page 106 of 872
REJ09B0325-0300