HD64F3048VTF8 Datasheet, PDF (796/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Appendix B Internal I/O Register
FLMCR—Flash Memory Control Register
Bit
7
6
5
4
V_PP
V_PP E


Initial value^* 0
0
0
0
Read/Write R
R/W


H'40
Flash memory
3
EV
0
R/W^*
2
PV
0
R/W^*
1
E
0
R/W^*
0
P
0
R/W^*
Program mode
0 Exit from program mode
(Initial value)
1 Transition to program mode
Erase mode
0 Exit from erase mode
1 Transition to erase mode
(Initial value)
Program-verify mode
0 Exit from program-verify mode
1 Transition to program-verify mode
(Initial value)
Erase-verify mode
0 Exit from erase-verify mode
1 Transition to erase-verify mode
(Initial value)
V_PP enable
0 V_PP pin 12 V power supply is disabled
(Initial value)
1 V_PP pin 12 V power supply is enabled
Programming power
0 Cleared when 12 V is not applied to V_PP
(Initial value)
1 Set when 12 V is applied to V_PP
Note: * The initial value is H'00 in modes 5, 6, and 7 (on-chip flash memory enabled). In modes
1, 2, 3, and 4 (on-chip flash memory disabled), this register cannot be modified and is
always read as H'FF.
H8/3048F
H8/3048B mask ROM version
H8/3048F-ONE
H8/3048ZTAT
H8/3048 mask ROM version
H8/3047 mask ROM version
H8/3045 mask ROM version
H8/3044 mask ROM version
Include this register
Not include this register
Rev. 3.00 Sep 27, 2006 page 768 of 872
REJ09B0325-0300