HD64F3048VTF8 Datasheet, PDF (353/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
Block Diagrams of Channels 3 and 4
Figure 10.4 is a block diagram of channel 3. Figure 10.5 is a block diagram of channel 4.
TCLKA to
TCLKD
φ, φ/2,
φ/4, φ/8
Clock selector
Comparator
Control logic
TIOCA₃
TIOCB₃
IMIA3
IMIB3
OVI3
Module data bus
Legend:
TCNT3:
Timer counter 3 (16 bits)
GRA3, GRB3: General registers A3 and B3 (input capture/output compare registers)
(16 bits × 2)
BRA3, BRB3: Buffer registers A3 and B3 (input capture/output compare buffer registers)
(16 bits × 2)
TCR3:
Timer control register 3 (8 bits)
TIOR3:
Timer I/O control register 3 (8 bits)
TIER3:
TSR3:
Timer interrupt enable register 3 (8 bits)
Timer status register 3 (8 bits)
Figure 10.4 Block Diagram of Channel 3
Rev. 3.00 Sep 27, 2006 page 325 of 872
REJ09B0325-0300