HD64F3048VTF8 Datasheet, PDF (553/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 14 Smart Card Interface
No parity error
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Output from transmitting device
Parity error
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
DE
Output from transmitting device
Legend:
Ds:
Start bit
D0 to D7: Data bits
Dp:
Parity bit
DE:
Error signal
Output from
receiving device
Figure 14.3 Smart Card Interface Data Format
The operating sequence is as follows.
1. When not in use, the data line is in the high-impedance state, and is pulled up to the high level
through a resistor.
2. To start transmitting a frame of data, the transmitting device transmits a low start bit (Ds),
followed by eight data bits (D0 to D7) and a parity bit (Dp).
3. Next, in the smart card interface, the transmitting device returns the data line to the high-
impedance state. The data line is pulled up to the high level through a resistor.
4. The receiving device performs a parity check. If there is no parity error, the receiving device
waits to receive the next data. If a parity error is present, the receiving device outputs a low
error signal (DE) to request retransmission of the data. After outputting the error signal for a
designated interval, the receiving device returns the signal line to the high-impedance state.
The signal line is pulled back up to the high level through the pull-up resistor.
5. If the transmitting device does not receive an error signal, it proceeds to transmit the next data.
If it receives an error signal, it returns to step 2 and transmits the same data again.
Rev. 3.00 Sep 27, 2006 page 525 of 872
REJ09B0325-0300