HD64F3048VTF8 Datasheet, PDF (727/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 21 Electrical Characteristics
21.3.3 Control Signal Timing
Control signal timing is shown as follows:
• Reset input timing
Figure 21.18 shows the reset input timing.
• Reset output timing
Figure 21.19 shows the reset output timing.
• Interrupt input timing
Figure 21.20 shows the input timing for NMI and IRQ₅ to IRQ₀.
• Bus-release mode timing
Figure 21.21 shows the bus-release mode timing.
φ
RES
MD₂ to MD₀
t_RESS
t_SR
t_MDS
t_RESS
t_SF
t_RESW
Figure 21.18 Reset Input Timing
φ
RESO
t_RESD
t_RESD
t_RESOW
Figure 21.19 Reset Output Timing^*
Note: * This is a function for models with on-chip mask ROM (H8/3048B, H8/3048, H8/3047,
H8/3045, and H8/3044), PROM (H8/3048ZTAT), and on-chip flash memory with a
dual power supply (H8/3048F). The function does not exist in the product with on-chip
flash memory with a single power supply (H8/3048F-ONE).
Rev. 3.00 Sep 27, 2006 page 699 of 872
REJ09B0325-0300