HD64F3048VTF8 Datasheet, PDF (235/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

I/O mode and idle mode
Section 8 DMA Controller
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value
Read/Write
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Transfer counter
In I/O mode and idle mode, ETCR functions as a 16-bit counter. The count is decremented by
1 each time one transfer is executed. The transfer ends when the count reaches H'0000.
Repeat mode
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
Bit
Undetermined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ETCRH
Transfer counter
7
6
5
4
3
2
1
0
Initial value
Read/Write
Undetermined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ETCRL
Initial count
In repeat mode, ETCRH functions as an 8-bit transfer counter and ETCRL holds the initial transfer
count. ETCRH is decremented by 1 each time one transfer is executed. When ETCRH reaches
H'00, the value in ETCRL is reloaded into ETCRH and the same operation is repeated.
The ETCRs are not initialized by a reset or in standby mode.
Rev. 3.00 Sep 27, 2006 page 207 of 872
REJ09B0325-0300