HD64F3048VTF8 Datasheet, PDF (256/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 8 DMA Controller
Table 8.8 Register Functions in Repeat Mode
Function
Register
Activated by
SCI0 Receive-
Data-Full
Interrupt
Other
Activation
Initial Setting
Operation
23
MAR
Destination
address
0 _register
Source
address
register
Destination or
source address
Incremented or
decremented at
each transfer
until H'0000,
then restored to
initial value
23
All 1s
7
0
IOAR
Source
address
register
Destination
address
register
Source or
destination
address
Held fixed
7
0
ETCRH
Transfer
counter
Transfer
counter
Number of
transfers
7
0
ETCRL
Initial transfer
count
Initial transfer Number of
count
transfers
Decremented
once per
transfer until
H'0000 is
reached, then
reloaded from
ETCRL
Held fixed
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
In repeat mode ETCRH is used as the transfer counter while ETCRL holds the initial transfer
count. ETCRH is decremented by 1 at each transfer until it reaches H'00, then is reloaded from
ETCRL. MAR is also restored to its initial value, which is calculated from the DTSZ and DTID
bits in DTCR. Specifically, MAR is restored as follows:
MAR ← MAR – (–1)^DTID · 2^DTSZ · ETCRL
ETCRH and ETCRL should be initially set to the same value.
In repeat mode transfers continue until the CPU clears the DTE bit to 0. After DTE is cleared to 0,
if the CPU sets DTE to 1 again, transfers resume from the state at which DTE was cleared. No
CPU interrupt is requested.
Rev. 3.00 Sep 27, 2006 page 228 of 872
REJ09B0325-0300