HD64F3048VTF8 Datasheet, PDF (523/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 13 Serial Communication Interface
In transmitting serial data, the SCI operates as follows.
1. The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
2. After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit in SCR is set to 1, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
a. Start bit: One 0 bit is output.
b. Transmit data: 7 or 8 bits are output, LSB first.
c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
d. Stop bit: One or two 1 bits (stop bits) are output.
e. Mark state: Output of 1 bits continues until the start bit of the next transmit data.
3. The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next
frame. If the TDRE flag is 1, the SCI sets the TEND flag in SSR to 1, outputs the stop bit, then
continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a transmit-end
interrupt (TEI) is requested at this time.
Figure 13.11 shows an example of SCI transmit operation using a multiprocessor format.
Multi-
processor
bit
Multi-
processor
bit
Start
1
bit
Data
Stop Start
bit bit
Data
Stop
bit
1
0 D0 D1
D7 0/1 1 0 D0 D1
D7 0/1 1
Idle (mark)
state
TDRE
TEND
TXI
request
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
TXI
request
TEI request
1 frame
Figure 13.11 Example of SCI Transmit Operation
(8-Bit Data with Multiprocessor Bit and One Stop Bit)
Rev. 3.00 Sep 27, 2006 page 495 of 872
REJ09B0325-0300