HD64F3048VTF8 Datasheet, PDF (798/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Appendix B Internal I/O Register
FLMCR2—Flash Memory Control Register 2
H'41
Flash memory
Bit
7
6
5
4
3
2
1
0
FLER







Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R/W
R/W
R/W R/W
R/W
R/W
R/W
Reserved bits
Flash memory error
0 Flash memory is operating normally. Flash memory program/erase
protection (error protection) is disabled.
(Initial value)
1 This indicates that an error has occurred during flash memory
programming/erasing. Flash memory program/erase protection
(error protection) is enabled.
Note: Bits 6 to 0 are reserved bits but are readable/writable.
H8/3048F-ONE
Include this register
H8/3048B mask ROM version Not include this register
H8/3048F
H8/3048ZTAT
H8/3048 mask ROM version
H8/3047 mask ROM version
H8/3045 mask ROM version
H8/3044 mask ROM version
Rev. 3.00 Sep 27, 2006 page 770 of 872
REJ09B0325-0300