HD64F3048VTF8 Datasheet, PDF (193/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 7 Refresh Controller
Bit 3—Address Multiplex Mode Select (M9/M8): Selects 8-bit or 9-bit column addressing.
The setting of this bit is valid when PSRAME = 0 and DRAME = 1. This bit is write-disabled
when the PSRAME or DRAME bit is set to 1.
Bit 3: M9/M8
0
1
Description
8-bit column address mode
9-bit column address mode
(Initial value)
Bit 2—Refresh Pin Enable (RFSHE): Enables or disables refresh signal output from the RFSH
pin. This bit is write-disabled when the PSRAME or DRAME bit is set to 1.
Bit 2: RFSHE
0
1
Description
Refresh signal output at the RFSH pin is disabled (the RFSH pin can be used
as a generic input/output port)
(Initial value)
Refresh signal output at the RFSH pin is enabled
Bit 1—Reserved: Read-only bit, always read as 1.
Bit 0—Refresh Cycle Enable (RCYCE): Enables or disables insertion of refresh cycles.
The setting of this bit is valid when PSRAME = 1 or DRAME = 1. When PSRAME = 0 and
DRAME = 0, refresh cycles are not inserted regardless of the setting of this bit.
Bit 0: RCYCE
0
1
Description
Refresh cycles are disabled
Refresh cycles are enabled for area 3
(Initial value)
Rev. 3.00 Sep 27, 2006 page 165 of 872
REJ09B0325-0300