HD64F3048VTF8 Datasheet, PDF (834/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Appendix B Internal I/O Register
RFSHCR—Refresh Control Register
H'AC Refresh controller
Bit
7
6
5
4
3
2
1
0
SRFMD PSRAME DRAME CAS/WE M9/M8 RFSHE  RCYCE
Initial value
0
0
0
0
0
0
1
0
Read/Write
R/W R/W R/W R/W R/W R/W

R/W
Refresh cycle enable
0 Refresh cycles are disabled
1 Refresh cycles are enabled for area 3
Refresh pin enable
0 Refresh signal output at the RFSH pin is disabled
1 Refresh signal output at the RFSH pin is enabled
Address multiplex mode select
0 8-bit column mode
1 9-bit column mode
Strobe mode select
0 2 WE mode
1 2 CAS mode
PSRAM enable, DRAM enable
Bit 6
Bit 5
PSRAME DRAME RAM Interface
0
0 Can be used as an interval timer
(DRAM and PSRAM cannot be
directly connected)
1 DRAM can be directly connected
1
0 PSRAM can be directly connected
1 Illegal setting
Self-refresh mode
0 DRAM or PSRAM self-refresh is disabled in software standby mode
1 DRAM or PSRAM self-refresh is enabled in software standby mode
Rev. 3.00 Sep 27, 2006 page 806 of 872
REJ09B0325-0300