HD64F3048VTF8 Datasheet, PDF (259/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 8 DMA Controller
8.4.5 Normal Mode
In normal mode the A and B channels are combined. One byte or word is transferred per request.
A designated number of these transfers are executed. Addresses are specified in MARA and
MARB. Table 8.9 indicates the register functions in I/O mode.
Table 8.9 Register Functions in Normal Mode
Register
Function
Initial Setting Operation
23
MARA
0 ^{Source address}
register
Source address
Incremented or
decremented once per
transfer, or held fixed
23
MARB
0 ^Destination
Destination
address register address
Incremented or
decremented once per
transfer, or held fixed
15
0 ^{Transfer counter Number of}
ETCRA
transfers
Decremented once per
transfer
Legend:
MARA: Memory address register A
MARB: Memory address register B
ETCRA: Execute transfer count register A
The source and destination addresses are both 24-bit addresses. MARA specifies the source
address. MARB specifies the destination address. MARA and MARB can be independently
incremented, decremented, or held fixed as data is transferred.
The transfer count is specified as a 16-bit value in ETCRA. The ETCRA value is decremented by
1 at each transfer. When the ETCRA value reaches H'0000, the DTE bit is cleared and the transfer
ends. If the DTIE bit is set, a CPU interrupt is requested at this time. The maximum transfer count
is 65,536, obtained by setting ETCRA to H'0000.
Figure 8.8 illustrates how normal mode operates.
Rev. 3.00 Sep 27, 2006 page 231 of 872
REJ09B0325-0300