HD64F3048VTF8 Datasheet, PDF (642/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
18.8.4 NMI Input Disable Conditions
While flash memory is being programmed/erased (P bit or E bit in FLMCR1 is set) and the boot
program is executing in the boot mode*¹, all interrupts including NMI input must be disabled
because the programming/erasing have priority.
This is done to avoid the following operation states:
1. Generation of an interrupt during programming/erasing violates the program/erase algorithms
and normal operation can not longer be assured.
2. Vector-read cannot be carried out normally*² during interrupt exception handling during
programming/erasing and the microcomputer runs away as a result.
3. If an interrupt is generated during boot program execution, the normal boot mode sequence
cannot be executed.
With above reasons, there are conditions that exceptionally disable NMI inputs only in the on-
board programming mode. However, this does not assure normal programming/erasing and
microcomputer operation.
Thus, when the flash memory is programmed/erased, all interrupt requests (exception handling
and bus release), including NMI, inside and outside the microcomputer, must be disabled. NMI
interrupt is also disabled in the error-protected state and when the P bit or E bit in FLMCR1 is
retained during flash memory emulation by RAM.
Notes: 1. Indicates the period up to branching to the on-chip RAM boot program area
(H'FFEF10). (This branch occurs immediately after programming control program
transfer was completed.)
Therefore, after branching to RAM area, NMI input is enabled in states other than the
program/erase state. Thus, interrupt requests inside and outside the microcomputer
must be disabled until initial writing by programming control program (writing of
vector table and NMI processing program, etc.) is completed.
2. In this case, vector read is not performed normally for the following two reasons:
• The correct value cannot be read even by reading the flash memory during
programming/erasing (P bit or E bit in FLMCR1 is set). (Value is undefined.)
• If a value has not yet been written to the interrupt vector table, interrupt exception
handling will not be performed correctly.
Rev. 3.00 Sep 27, 2006 page 614 of 872
REJ09B0325-0300