HD64F3048VTF8 Datasheet, PDF (714/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 21 Electrical Characteristics
Table 21.18 Timing of On-Chip Supporting Modules
Condition A: V_CC = 3.0 V to 3.6 V, AV_CC = 3.0 V to 3.6 V, V_REF = 3.0 V to AV_CC,
V_SS = AV_SS = 0 V, φ = 2 MHz to 25 MHz, T_a = –20°C to +75°C (regular
specifications), T_a = –40°C to +85°C (wide-range specifications)
Condition B: V_CC = 5.0 V ±10%, AV_CC = 5.0 V ±10%, V_REF = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, φ = 2 MHz to 25 MHz, T_a = –20°C to +75°C (regular
specifications), T_a = –40°C to +85°C (wide-range specifications)
Item
DMAC DREQ setup time
DREQ hold time
TEND delay time 1
TEND delay time 2
ITU Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock Single edge
pulse width _{Both edges}
SCI Input clock Asynchronous
cycle
Synchronous
Input clock rise time
Input clock fall time
Input clock pulse width
Transmit data delay time
Receive data setup time
(synchronous)
Receive
data hold
time (syn-
chronous)
Clock input
Clock output
Symbol
t_DRQS
t_DRQH
t_TED1
t_TED2
t_TOCD
t_TICS
t_TCKS
t_TCKWH
t_TCKWL
t_SCYC
t_SCYC
t_SCKr
t_SCKf
t_SCKW
t_TXD
t_RXS
t_RXH
t_RXH
Condition A
25 MHz
Min Max
20
—
10
—
—
50
—
50
—
50
40
—
40
—
1.5 —
2.5 —
4
—
6
—
—
1.5
—
1.5
0.4 0.6
—
100
100 —
100 —
0
—
Condition B
25 MHz
Min Max Unit
20
—
ns
10
—
—
50
—
50
—
50
ns
40
—
40
—
1.5 —
t_CYC
2.5 —
4
—
t_CYC
6
—
—
1.5
—
1.5
0.4
0.6
t_SCYC
—
100 ns
100 —
Test
Conditions
Figure 21.30
Figures 21.28
and 21.29
Figure 21.24
Figure 21.25
Figure 21.26
Figure 21.27
100 —
0
—
Ports Output data delay time
t_PWD
—
50
—
50
ns
Figure 21.23
and _{Input data setup time}
TPC
t_PRS
50
—
50
—
Input data hold time
t_PRH
50
—
50
—
Rev. 3.00 Sep 27, 2006 page 686 of 872
REJ09B0325-0300