HD64F3048VTF8 Datasheet, PDF (636/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
If erasing multiple blocks, set a single bit in EBR for the next block to be erased, and repeat the
erase/erase-verify sequence as before.
Start
*1
Set SWE bit in FLMCR1
Wait (t_sswe) µs
Perform erasing in block units.
*5
n=1
Set EBR
*3, *4
Enable WDT
Set ESU bit in FLMCR1
Wait (t_sesu) µs
Set E bit in FLMCR1
Wait (t_se) ms
Clear E bit in FLMCR1
Wait (t_ce) µs
Clear ESU bit in FLMCR1
Wait (t_cesu) µs
Disable WDT
*5
Start of erase
*5
Erase halted
*5
*5
Set EV bit in FLMCR1
Wait (t_sev) µs
*5
Set block start address as verify address
n←n+1
H'FF dummy write to verify address
Wait (t_sevr) µs
*5
Increment
address
No
Read verify data
Verify data = all 1s?
Yes
Last address of block?
Yes
Clear EV bit in FLMCR1
*2
No
*5
Wait (t_cev) µs
Clear SWE bit in FLMCR1
*5
Wait (t_cswe) µs
Clear EV bit in FLMCR1
Wait (t_cev) µs
*5
n ≥ N?
Yes
Clear SWE bit in FLMCR1
Wait (t_cswe) µs
*5
No
*5
End of erasing
Erase failure
Notes: 1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Verify data is read in 16-bit (word) units.
3. Make only a single-bit specification in the erase block register (EBR). Two or more bits must not be set simultaneously.
4. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
5. The wait times and the value of N are shown in section 21.1.6, Flash Memory Characteristics.
Figure 18.14 Erase/Erase-Verify Flowchart (Single-Block Erasing)
Rev. 3.00 Sep 27, 2006 page 608 of 872
REJ09B0325-0300