HD64F3048VTF8 Datasheet, PDF (163/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 6 Bus Controller
6.3.2 Chip Select Signals
For each of areas 7 to 0, the H8/3048B Group can output a chip select signal (CS₇ to CS₀) that goes
low to indicate when the area is selected. Figure 6.3 shows the output timing of a CS_n signal (n = 0
to 7).
Output of CS₃ to CS₀: Output of CS₃ to CS₀ is enabled or disabled in the data direction register
(DDR) of the corresponding port.
In the expanded modes with on-chip ROM disabled, a reset leaves pin CS₀ in the output state and
pins CS₃ to CS₁ in the input state. To output chip select signals CS₃ to CS₁, the corresponding DDR
bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins CS₃ to
CS
0
in
the
input
state.
To
output
chip
select
signals
CS
3
to
CS₀,
the
corresponding
DDR
bits
must
be set to 1. For details see section 9, I/O Ports.
Output of CS₇ to CS₄: Output of CS₇ to CS₄ is enabled or disabled in the chip select control
register (CSCR). A reset leaves pins CS₇ to CS₄ in the input state. To output chip select signals CS₇
to CS₄, the corresponding CSCR bits must be set to 1. For details see section 9, I/O Ports.
φ
Address
bus
External address in area n
CS_n
Figure 6.3 CS_n Output Timing (n = 7 to 0)
When the on-chip ROM, on-chip RAM, and internal I/O registers are accessed, CS₇ and CS₀
remain
high.
The
CS
n
signals
are
decoded
from
the
address
signals.
They
can
be
used
as
chip
select signals for SRAM and other devices.
Rev. 3.00 Sep 27, 2006 page 135 of 872
REJ09B0325-0300