HD64F3048VTF8 Datasheet, PDF (497/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 13 Serial Communication Interface
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from TDR into TSR and the next serial transmit data can be written in TDR.
Bit 7: TDRE
0
1
Description
TDR contains valid transmit data
[Clearing conditions]
• Software reads TDRE while it is set to 1, then writes 0.
• The DMAC writes data in TDR.
TDR does not contain valid transmit data
(Initial value)
[Setting conditions]
• The chip is reset or enters standby mode.
• The TE bit in SCR is cleared to 0.
• TDR contents are loaded into TSR, so new data can be written in TDR.
Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains new receive data.
Bit 6: RDRF
Description
0
RDR does not contain new receive data
(Initial value)
[Clearing conditions]
• The chip is reset or enters standby mode.
• Software reads RDRF while it is set to 1, then writes 0.
• The DMAC reads data from RDR.
1
RDR contains new receive data
[Setting condition]
When serial data is received normally and transferred from RSR to RDR.
Note:
The RDR contents and RDRF flag are not affected by detection of receive errors or by
clearing of the RE bit to 0 in SCR. They retain their previous values. If the RDRF flag is still
set to 1 when reception of the next data ends, an overrun error occurs and receive data is
lost.
Rev. 3.00 Sep 27, 2006 page 469 of 872
REJ09B0325-0300