HD64F3048VTF8 Datasheet, PDF (452/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 11 Programmable Timing Pattern Controller
Different Triggers for TPC Output Groups 2 and 3
If TPC output groups 2 and 3 are triggered by different compare match events, the address of the
upper 4 bits of NDRB (group 3) is H'FFA4 and the address of the lower 4 bits (group 2) is
H'FFA6. Bits 3 to 0 of address H'FFA4 and bits 7 to 4 of address H'FFA6 are reserved bits that
cannot be modified and are always read as 1.
Address H'FFA4
Bit
7
6
5
4
3
2
1
0
NDR15 NDR14 NDR13 NDR12 



Initial value
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W




Next data 15 to 12
These bits store the next output
data for TPC output group 3
Reserved bits
Address H'FFA6
Bit
7
6
5
4
3
2
1
0



 NDR11 NDR10 NDR9 NDR8
Initial value
1
1
1
1
0
0
0
0
Read/Write




R/W
R/W
R/W R/W
Reserved bits
Next data 11 to 8
These bits store the next output
data for TPC output group 2
Rev. 3.00 Sep 27, 2006 page 424 of 872
REJ09B0325-0300